The fast development of the integrated circuit not only improves many technologies but also largely increases the importance of computer and several kinds of electrical consumer products. People have changed their living styles and the development of the related technologies increases the working efficiency of industry and government. The memory plays an important role in the application of integrated circuit because it can temporarily or permanently store data and programs.
As the process of chip becomes more precise and has higher clock, the difficulty and complexity of the testing increase as well. Testing cost has been an important production cost that cannot be neglected. While in the system chip, a great number of and different kinds of memories also increase the testing cost.
The present memory test process is to input test order individually from automatic test equipment (ATE) and to construct a complete test process. However, the control and communication complexity between the memory to be tested and outer automatic test equipment will be increased, and the testing time will be longer using this method.
Thus the present technique puts a built-in self-test (BIST) circuit in the memory to be tested to improve the disadvantage of inputting test order individually. Then the test algorithm in the build-in self-test circuit processes reading and writing actions on the memory to be tested. Although this method reduces the complexity to communicate with the outer test equipment, to ensure memory in the product to work normally and stably, few test algorithms in the built-in self-test circuit is not enough to achieve the required fault coverage. If all of the test algorithms are built in the test circuits, the area cost of the chip will be highly increased. So analyzing test algorithms and deleting redundant test algorithms are necessary steps to shorten test time and to save chip area.
In addition, after manufacturing system chip, the test algorithm will still need to be adjusted or to be added based on different test requirements to perform further test and verification on the product. Here a screening and analyzing structure is needed to analyze if the adjusted or added algorithms can be supported by the built-in self-test circuit in the chip. The screening and analyzing structure can effectively and rapidly screen out the test algorithm supported by the built-in self-test circuit to reach the targets of reducing product verification schedule and shortening time for product to appear on market.